This book addresses reliability and energy efficiency of on-chip networks using cooperative error control. It describes an efficient way to construct an adaptive error control codec capable of tracking noise conditions and adjusting the error correction strength at runtime.

Introduction.- Existing Transient and Permanent Error Management in NoCs.- Adaptive Error Control Coding at Datalink Layer.- Transient and Permanent Link Errors Co-Management.- Dual-Layer Cooperative Error Control for Transient Error.- A Flexible Parallel Simulator for Networks-on-Chip with Error Control.- Conclusions and Future Directions. 

This book addresses reliability and energy efficiency of on-chip networks using a configurable error control coding (ECC) scheme for datalink-layer transient error management. The method can adjust both error detection and correction strengths at runtime by varying the number of redundant wires for parity-check bits. Methods are also presented to tackle joint transient and permanent error correction, exploiting the redundant resources already available on-chip. A parallel and flexible network simulator is also introduced, which facilitates examining the impact of various error control methods on network-on-chip performance.Includes a complete survey of error control methods for reliable networks-on-chip, evaluated for reliability, energy and performance metrics; Provides analysis of error control in various network-on-chip layers, as well as presentation of an innovative multi-layer error control coding technique;Presents state-of-the-art solutions to address simultaneously reliability, energy and performance;Describes configurable error management solutions and their hardware implementation details for variable noise conditions; Provides details of a flexible and parallel NoC simulator and corresponding simulation setup to achieve the reported results.  

Includes a complete survey of error control methods for reliable networks-on-chip, evaluated for reliability, energy and performance metrics Presents state-of-the-art solutions to address simultaneously reliability, energy and performance Provides hardware implementation details of error control in networks-on-chip Provides details of a parallel simulator and corresponding simulation setup to achieve the reported results

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