Timing research in high performance VLSI systems has advanced at a steady pace over the last few years. Tools, however, especially theoretical mechanisms, lag behind. Much of the present timing research relies heavily on timing diagrams which, although intuitive, are inadequate for analysis of large designs with many parameters. Further, timing diagrams offer only approximations, not exact solutions to many timing problems and provide little insight in the cases where temporal properties of a design interact intricately with the design's logical functionalities. This text presents a methodology for timing research which facilitates analysis and design of circuits and systems in a unified temporal and logical domain. The book aims to present the central idea of representing logical and timing information in a common structure, (TBFs), and to present a canonical form suitable for efficient manipulation. This methodology is then applied to practical applications to provide intuition and insight into the subject so that these general methods can be adapted to specific engineering problems and also to further the research necessary to enhance the understanding of the field. The text is written for professionals involved in timing research and digital designers who want to enhance their understanding of the timing aspects of high-speed circuits. The prerequisites are a common background in logic design, computer algorithms, combinatorial optimization and a certain degree of mathematical sophistication.