It focuses on hardware Trojan detection and prevention and counterfeit detection and prevention. The authors discuss a variety of detection schemes and design methodologies for improving Trojan detection techniques, as well as various attempts at developing hardware Trojans in IP cores and ICs.

Introduction.- Hardware Trojan Detection: Untrusted Third-party IP Cores.- Hardware Trojan Detection: Untrusted Manufactured Integrated Circuits.- Design for Hardware Trust: Dummy Scan Flip-flop Insertion.- Design for Hardware Trust: Layout-aware Scan Cell Reordering.- Design for Hardware Trust: Ring Oscillator Network.- Design Vulnerability Analysis.- Trojan Prevention: Built-In Self-Authentication.- Counterfeit Ics: Taxonomies, Assessment, and Challenges.- Counterfeit Ics: Detection and Prevention of Recycled Ics Using On-chip Sensors.- Counterfeit Ics: Pathy-Delay Fingerprinting.

This book provides readers with a comprehensive introduction to hardware Trojans.  The authors explain the hardware Trojan taxonomy in detail, while delivering deep understanding of the potential impacts throughout the integrated circuit (IC) lifecycle. While discussing the shortcomings of current, industrial IC testing techniques for hardware Trojans, the authors describe the details of emerging techniques to detect them and to prevent their insertion into products. ·         Provides a comprehensive introduction to hardware Trojans and their potential impact on the integrated circuit lifecycle;·         Equips designers with tools for identifying potential vulnerabilities throughout the design cycle and manufacturing;·         Describes state-of-the-art techniques for hardware Trojan design, detection, and prevention;·         Analyzes susceptibility at the behavioral-, gate-, layout-level to Trojan insertion.

Provides a single-source reference to hardware Trojans and counterfeit detection in integrated circuits Equips designers with architecture-level solutions to improve detection and prevention of hardware Trojans and counterfeits Enables a strategy of silicon design authentication to verify the trustworthiness manufactured chips, validating the chip’s conformance with the original functional and performance specifications Includes supplementary material: sn.pub/extras